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MXED101
30V, 192-Channel OLED Display Driver
Features: * CMOS technology * 192 Precision outputs * Programmable output current control * Optimized adjacent channel and chip-to-chip output matching * 3.3V or 5V logic supply voltage * 55 MHz clock frequency * Cascadable * 30V output driver supply voltage * Bi-directional data transfer * Supports Grayscale, Binary, and Standby modes * Low power consumption * Package type: TCP (MXED101TP) and Die (MXED101DI) General Description
The MXED101 is a 6-bit, 192-output column driver IC designed to drive passive matrix full-color (RGB) and monochrome Organic Light Emitting Diode (OLED) displays. Each of the 192 current outputs is designed to act as a precision high impedance current source. The MXED101 current source output supply range is from 15 to 30V. The outputs are arranged in a row on one side of the die with a pitch of 92 microns, which facilitates easy interface with the display. The MXED101 consists of an Input Register, Transfer Latch, Comparator, Bi-directional Shift Register, Counter, and 192 Programmable Current Outputs. The device has three 6-bit input data buses, DA(5-0), DB(5-0), and DC(5-0), to accept RGB or monochrome data. This data can be clocked through the device at a maximum speed of 55 MHz with a 5V logic supply (40 MHz with a 3.3V logic supply). The outputs of the MXED101 are arranged in three programmable interdigitized banks (A, B, and C) of 64 outputs each, a bank for each color of the RGB data (programming the output current is described in the Functional Description section). Bank A controls outputs 1, 4, 7, ..., 190; Bank B controls outputs 2, 5, 8, ..., 191; and Bank C controls outputs 3, 6, 9, ..., 192. The MXED101 employs three methods to adjust display brightness: a global gain voltage, a 3-bit digital control for each color, and an external 10.8 KW resistor. In addition to these methods, the relative brightness of each output can be controlled by onchip pulse width modulation. A standby signal (STBY) is provided to place the display in low power standby mode whenever it is necessary.
Ordering Information Part # MXED101 Description 30V, 192-Channel OLED Display Driver
Block Diagram
SWC DA(5-0) DB(5-0) DC(5-0) CLKSH Q1 192 X 6 Input Register 192 x 6 Transfer Latch Program- Q2 mable Q3 . 192- . . channel . . Output . . Terminal Q192 Q1 Q2 Q3
192 x 6
Comparator
Q192
DIRTKN RTKNB LTKNB LE CLKEX STBY SDM(1-0) GG GA(2-0) GB(2-0) GC(2-0) RG
64 x 1 BiDirection Shift Register
6-Bit Up Counter
Output Mapping/ Current Programming
DS-MXED101-R9
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MXED101
Absolute Maximum Ratings (Vss=OV)
Parameter Logic Supply Voltage Analog Supply Voltage Logic Input Voltage Storage Temperature Symbol VCC VDD VLIN TSTG Rating -0.3 to 7.0 -.3 to 35.0 -.3 to VCC+.3 -55 to 125 Unit Vdc Vdc Vdc C
Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and effect its reliability.
Electrical Characteristics
Parameter Logic Supply Voltage Analog Supply Voltage GG Voltage External RGPin Resistor High Logic Input Level Low Logic Input Level High Logic Level Input Current Low Logic Level Input Current High Logic Output Level Low Logic Output Level Logic Supply Current Analog Supply Current** Operating Temperature (Junction) Symbol VCC VDD VGG RRG VIH VIL IIH IIL VOH VOL Icc IDD TJ Test Conditions Min 3.0 15 0 -0.1% Vcc - 0.6 -0.2 -10 -10 Vcc-0.2 Max 5.5 30 12 +0.1% Vcc + 0.2 .6 10 10 0.2 7 6.0 + Iout 100 Units Vdc Vdc Vdc 10.8K Vdc Vdc A A V V mA mA C
VDD 15V
IOH>-10A IOL<10A
20
**Analog supply current is highly dependable on the output current of the 192 output channels (Iout), which is determined by the application. Note: Vdout, Ibank, and Idie are transferred to the output parameters channels table.
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Rev. 9
MXED101
Digital Timing for Vcc in Range of 4.5 to 5.5 VDC
Parameter Shift Clock Frequency (VCC=4.5 + 5.5V) Shift Clock Frequency (VCC=3.0 to 4.4V) Shift Clock Frequency Pulse Width (VCC=4.5 + 5.5V) Shift Clock Frequency Pulse Width (VCC=3.0 to 4.4V) Shift Clock Frequency Duty Cycle Shift Clock to Latch Delay Exposure Clock Frequency Exposure Clock Pulse Width Exposure Duty Cycle Data Setup Time Data Hold Time Token Setup Time Token Hold Time Token Bit Output Delay Token Bit Pulse Width Latch Pulse Width Last data to Latch Enable Time Latch Disable to Exposure Clock Time Exposure Clock to Latch Enable Time Standby to Ready Time Symbol fCLK tSPW tSPW DCSCK tDSKL fEKF tEPW DCEX tDSU tDHD tTSU ttHD tSTD tTPW tLAPW tDLD tLED tDLE tSTBY Min Typ Max 55 40 Units MHz MHz nS nS 60 10 500 60 -- -- -- -- 13 -- -- -- -- -- 10 % nS MHz nS % nS nS nS nS nS nS nS nS nS nS mS
7 9.6 40 3 (clock Cycles)
22 30 50
40 5 5 5 5 -- 15 50 200 50 50
40 50 -- -- -- -- -- -- -- -- -- --
Output Channel Parameters
Parameter Driver Output Voltage Compliance Per bank max to min channel output current ratio High output die to low output die average output current ratio Output Current Rise Time Output Current Fall Time Output Current Settling Time Exposure Clock to Output High Delay Exposure Clock to Output Low Delay Channel output current rise/fall time Shorting Switch Resistance Symbol VQn IBANK IDIE tIOR tIOF tIOS tOHD tOLD tIORF Typ O1.0 1.0 _ _ _ _ _
Rev. 9
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MXED101
Signal Definition
Name VDD VCC GND ISHRT RSTB CLKSH I I I/0/A Description Power supply for the 192 current driver output channels - 6 pads Low voltage logic power supply - 2 pads Ground - 4 pads Ground used to short the 192 current driver output channels - 4 pads. Note: There can be high currents on this line. It should be seperated from the circuit ground pads (GND) to prevent ground bounce. Reset: Active low signal used to reset digital logic for test purposes. This input is pulled high internally. Token Shift Clock: Used to shift tokens down the length of the driver IC. The direction of token shift is determined by DIRTKN pin. It is possible to load only a portion of the 192 output channels prior to latching in applications not requiring the full 192 channels. The speed of the clock is from DC to 55 MHz at 5V logic power supply (40 MHz at 3.3V). Left Token Bit: Used to pass the tokens into and out of the driver IC. The pin is used as input for shift right and as output for shift left. High state represents the presence of token. The shifting is performed from DC to 55 MHz (40 MHz at 3.3V). Right Token Bit: Used to pass the tokens into and out of the driver IC. The pin is used as input for shift left and as output for shift right. High state represents the presence of token. The shifting is performed from DC to 55 MHz (40 MHz at 3.3V). Token Direction: Used to determine the shift direction of the token. When the signal is high, causes the token to shift left to right (1->64) and when the signal is low causes the token to shift to left (64->1). This input is pulled high internally. The token shifts 3 cells at a time to account for the 3 parallel data inputs. Latch Enable: Active high signal used to latch RGB data from the driver outputs into a set of transfer latches. Once a line of data is latched into the transfer latch, OLED exposure can begin. At the same time, a new line of exposure data can be loaded into the input register of the driver IC. On the rising edge of the of LE, all token registers are cleared, the exposure counter is asynchronously preset to a low state and exposure data is allowed to pass from the input register to the transfer latch. On the falling edge of LE, the exposure counter and output drivers are enabled within tLED (50 ns). 6-bit Data input A. Signal bus used for the exposure data input word for outputs 1,4,7,...,190. The driver performs at clock speed from DC to 55 MHz (40 MHz at 3.3V). 6-bit Data input B. Signal bus used for the exposure data input word for outputs 2,5,8,...,191. The driver performs at clock speed from DC to 55 MHz (40 MHz at 3.3V). 6-bit Data input C. Signal bus used for the exposure data input word for channels 3,6,9,...,192. The driver performs at clock speed from DC to 55 MHz (40 MHz at 3.3V). Exposure Clock: Signal (DC to 10 MHz signal) used to clock the input of the driver ICs exposure counter (6-bits). The signal is used to cycle the driver IC internal counter from 0 up to 63. The signal must be cycled at least 64 times between LE pulses to completely cycle the counter. The first rising edge of CLKEX will enable all non zero outputs without changing the counter. Additional rising edges of CLKEX will increment the counter. When the counter and data of values for an output match, the output is disabled until LE re-enables the exposure counter. Cycles of CLKEX beyond 64 will have no effect until the next cycle of LE re-enables the counter. Binary/Grayscale: Signal used to determine if the driver IC is either 6 bit grayscale or binary. Low -> grayscale. High -> Binary. This input is internally pulled to a logic low. Global Gain: Used to set the global current gain. The voltage range on this pin is 0V to 12V when VDD is 15V. The base current level is GG/RG, with a peak base current level of 1.455mA. This input is internally pulled to a logic low.
LTKNB
I/O
RTKNB
I/O
DIRTKN
I
LE
I
DA(5-0) DB(5-0) DC(5-0) CLKEX
I I I I
TGR GG
I A
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Rev. 9
MXED101
Signal Definition (continued)
Name RG GA(2-0) GB(2-0) GC(2-0) STBY SDM(1-O) I/0/A A I I I I I Description Resistor Gain: Used to set the global current gain. A precision resistor shall be connected from this node to analog ground which, in conjunction with the GG input voltage, sets up the base current level of the chip. A Gain: Used to set the current on driver output channels 1,4,7,...,190. This input is internally pulled to a logic low. B Gain: Used to set the current on driver output channels 2,5,8,...,191. This input is internally pulled to a logic low. C Gain: Used to set the current on driver output channels 3,6,9,...,192. This input is internally pulled to a logic low. Standby Reset: Active high signal used to place the IC in a low power standby mode. When in the high state the IC is non-functional and power dissipation is minimized. This input is internally pulled to a logic low. Stripe/Diagonal/Mosaic: These input signals are used to modify the output channel current levels depending on which row of the display is active. The falling edge of LE is used to modify the A, B, C channels. When the STBY is set to a logic high, the A, B, C channel outputs are reset to their initial mapping. These inputs are internally pulled to a logic high. (See the SDM function below). Switch Channels: This input signal is used to control when the individual output channels are in the tri-state condition (current is not sourced and the switch to ground is off). When the SWC input is in the high state, each output channel turns the switch to ground on as soon as the data count is matched and current source disabled. When SWC is in the low state, each channel remains in the tri-state condition from when the current source is disabled until the counter equals 63. This input is internally pulled to a logic low. These pins should be left open circuited. These pins should be left open circuited. OLED current source driver outputs.
SWC
I
TST(9-0) TEST(2-0) Q1-Q192
I A A
Note: A= > analog, I= > digital input, O= > digital output
Rev. 9
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MXED101
Functional Description Output Current Hold-On-Time Control There are two modes for controlling the 192 outputs current hold-on-times: 1- Grayscale: The grayscale is obtained when the TGR pin is low or open. Each of the three banks has a 6-bit control word, DA(5-0), DB(5-0), and DC(5-0), that is updated at the CLKSH signal clock which allows each output to turn on for a period of 0 to 63 counts of the CLKEX signal clock. 2- Binary Mode: Binary mode is obtained when the TGR input signal is high. Data is loaded in a similar way that is described in the grayscale mode. After the data is latched the DA5, DB5, or DC5 data bit is gated with CLKEX to determine the on or off status of the output drivers.
Output Current Magnitude Control GG, RG, GA(2-0), GB(2-0), and GC(2-0) controls the output current of the output drivers in the three banks. A precision 10.8 K (+/- 0.1%) resistor is tied from RG to ground. A voltage between 0.5 and 12V is applied to GG to adjust the overall brightness of the display. GA(2-0), GB(2-0), and GC(2-0) are 3-bit logic inputs that control the relative brightness of the A, B, and C banks output drivers respectively. The total output driver current is limited to a maximum of 0.6 mA for each output. Below this limit, the individual output current for banks A, B, and C is programmed as follows: I(out) = V(GG) 10.8 Kohms Where: x F(gain) 16 = 5.79E-6 *V(GG)*F(gain)
GA/GB/GC (2-0) 0x7 0x6 0x5 0x4
F(gain) 31 26 22 19
GA/GB/GC (2-0) 0x3 0x2 0x1 0x0
F(gain) 16 14 12 10
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Rev. 9
MXED101
Functional Description (continued) Output Current Turn-Off Control The SWC input signal controls turn-off of the driver outputs. When the SWC signal is high, each output is switched to ground when the data count is matched and simultaneously disables the current source. When SWC is low, each output remains in a tri-state condition from when the current source is disabled until the counter equals 63. SDM Function The SDM1 and SDM0 inputs determine how the A, B, and C display output banks are configured. They may also be used to generate special effects in the display. When the SDM signals are open or high, the MXED101 is in its normal operating mode (stripe mode). The SDM mapping to screen configuration is updated each time LE goes high and is as follows:
SDM1 1 1 0 0
SDM0 1 0 1 0
Mode Stripe Diagonal Mosaic Intv Mosaic
Line 1 ABC ABC BCA ABC
Line 2 ABC CAB BCA BCA
Line 3 ABC BCA BCA ABC
Line 4 ABC ABC BCA BCA
Line 5 ABC CAB BCA ABC
Line 6 ABC BCA BCA BCA
Note: there is no effect on the DA, DB, DC data buses and which banks they load. Under all SDM1, 0 conditions, DA loads banks 1,4,7,...,190, DB loads banks 2,5,8,...,191, and DC loads banks 3,6,9,...,192.
Rev. 9
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MXED101
Die Size and Pad Locations:
ISHRT ISHRT PIN 70 IOUT1 PIN 71 (0,0) AT CENTER OF PIN 70
TEST(0)
TEST(1)
LTKNB PIN 60
GND
VDD
VDD
VDD
RG
GG
PIN 59 VCC GND
Y
CLKSH CLKEX LE TST(9) TST(8) STBY DA(0) DA(1) DA(2) DA(3) DA(4) DA(5) DB(0) DB(1) DB(2) DB(3) DB(4) DB(5) DC(0) DC(1)
X
REST OF 192 CHANNEL OUTPUT PADS
Q192 PIN 262 ISHRT TEST(2) VDD
MXED101 DIE PINOUT
NOT TO SCALE
DC(2) DC(3) DC(4) DC(5) GC(0) GC(2) GB(0) GB(2) GA(0) GA(2) TGR SWC VCC
RSTB SMD(0) SMD(1) GC(1) GB(1) GA(1) DIRTKN GND
TST(7) TST(6)
TST(5) TST(4) TST(3) TST(2) TST(1) PIN 10 ISHRT PIN 1 VDD RTKNB PIN 9 VDD TST(0) GND
Die size is 18,7856 x 2,684 microns
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Rev. 9
MXED101
MXED101 Product Description
Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 71-262 Name ISHRT ISHRT TEST(2) VDD VDD VDD TST(0) GND RTKNB TST(1) TST(2) TST(3) TST(4) TST(5) TST(6) TST(7) GND DIRTKN GA(1) GB(1) GC(1) SDM(1) SDM(0) RSTB VCC SWC TGR GA(2) GA(0) GB(2) GB(0) GC(2) GC(0) DC(5) DC(4) Q(1-192) Pad Location (in microns) Pad Name 18392,338 36 DC(3) 18392,511 37 DC(2) 18392,693 38 DC(1) 18392,854 39 DC(0) 18392,1027 40 DB(5) 18392,1201 41 DB(4) 18392,1383 42 DB(3) 18392,1543 43 DB(2) 18392,1805 44 DB(1) 17997,2352 45 DB(0) 17823,2352 46 DA(5) 17650,2352 47 DA(4) 17476,2352 48 DA(3) 17302,2352 49 DA(2) 15086,2352 50 DA(1) 14910,2352 51 DA(0) 14736,2352 52 STBY 14542,2352 53 TST(8) 14368,2352 54 TST(9) 14195,2352 55 LE 14021,2352 56 CLKEX 13848,2352 57 CLKSH 13674,2352 58 GND 13500,2352 59 VCC 13327,2352 60 LTKNB 13153,2352 61 GND 12980,2352 62 GG 12806,2352 63 RG 12632,2352 64 VDD 12459,2352 65 VDD 12285,2352 66 VDD 12112,2352 67 TEST(0) 11938,2352 68 TEST(1) 11730,2352 69 ISHRT 11501,2352 70 ISHRT 427 + 92*(N-1), 129 where N =1 to 192 Pad Location (in microns) 11272,2352 11042,2352 10814,2352 10584,2352 7781,2352 7552,2352 7322,2352 7093,2352 6864,2352 6635,2352 6406,2352 6232,2352 6058,2352 5885,2352 5711,2352 5538,2352 1920,2352 1747,2352 1573,2352 1400,2352 1226,2352 1052,2352 209,2352 35,2352 0,1739 0,1543 0,1383 0,1214 0,1032 0,858 0,685 0,524 0,356 0,182 0,0
Note: Pad location reference is to bottom left-hand corner.
Rev. 9
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MXED101
Timing Diagrams - Load Data Pattern Timing
LOAD DATA PATTERN MACRO TIMING
1 DIE DISPLAY - LOAD ONE 64 BIT PATTERN FROM LEFT
64 DATA CYCLES CLKSH LTKNB (IN) RTKNB (OUT) LE DA/DB/DC(5-0) 64 CLKEX 1 64 1 64 1
N DIE DISPLAY - LOAD N 64 BIT PATTERNS FROM LEFT
N * 64 DATA CYCLES CLKSH LTKNB - 1ST DIE RTKNB - 1ST DIE LE DA/DB/DC(5-0) N*64 CLKEX 1 LOAD 1ST DIE LOAD 2ND DIE LOAD NTH DIE 64 1 64 128 N*64 1
FIGURE 2
TIMING1 MICRONIX INTEGRATED SYSTEMS INC A
Aliso Viejo, California 62656
SCALE
SIZE
PROJ/PROD NO.
FSCM NO.
DWG NO.
REV
MXHV101
0F4G3
11133
SHEET
-
B 1
LOAD DATA PATTERN TIMING
LOADING DATA FROM LEFT CLKSH tTSU LTKNB (IN) tSTD RTKNB (OUT) tDLD LE tLAPW DA/DB/DC(5-0) N*64 tDLE CLKEX 64 1 1 tLED tDSU tDHD tLDD tSTD tTPW tTHD
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Rev. 9
MXED101
Application note:
CLKSH LE DA/DB/DC(5-0) CLKEX TGR GA/GB/GC(2-0) SWC 12V GG
NOTE: DATA ORDER FOR DA/DB/DC (5-0) WOULD BE 1-192, 386-576, 577-768, 193-384
VCC
DIRTKN LTKNB RTKNB MXED101 10.8K 10.8K
CHAN 1 - 192
LTKNB MXED101
CHAN 385 - 576
RTKNB
TOKEN BIT
ARRAY OF N SWITCHES TO GND
ROW DATA
NROWS
ORGANIC LIGHT EMITING DIODE ARRAY 768 X N ELEMENTS
CHAN 193 - 384
CHAN 577 - 768
MXED101 DIRTKN RTKNB LTKNB
10.8K
MXED101
RTKNB
Rev. 9
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10.8K
11
MXED101
Notes:
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Rev. 9
MXED101
Notes:
Rev. 9
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Worldwide Sales Offices
CLARE LOCATIONS
Clare Headquarters 78 Cherry Hill Drive Beverly, MA 01915 Tel: 1-978-524-6700 Fax: 1-978-524-4900 Toll Free: 1-800-27-CLARE Clare Micronix Division 145 Columbia Aliso Viejo, CA 92656-1490 Tel: 1-949-831-4622 Fax: 1-949-831-4628
EUROPE
European Headquarters CP Clare nv Bampslaan 17 B-3500 Hasselt (Belgium) Tel: 32-11-300868 Fax: 32-11-300890 France Clare France Sales Lead Rep 99 route de Versailles 91160 Champlan France Tel: 33 1 69 79 93 50 Fax: 33 1 69 79 93 59 Germany Clare Germany Sales ActiveComp Electronic GmbH Mitterstrasse 12 85077 Manching Germany Tel: 49 8459 3214 10 Fax: 49 8459 3214 29 Italy C.L.A.R.E.s.a.s. Via C. Colombo 10/A I-20066 Melzo (Milano) Tel: 39-02-95737160 Fax: 39-02-95738829 Sweden Clare Sales Comptronic AB Box 167 S-16329 Spanga Tel: 46-862-10370 Fax: 46-862-10371 United Kingdom Clare UK Sales Marco Polo House Cook Way Bindon Road Taunton UK-Somerset TA2 6BG Tel: 44-1-823 352541 Fax: 44-1-823 352797
ASIA PACIFIC
Asian Headquarters Clare Room N1016, Chia-Hsin, Bldg II, 10F, No. 96, Sec. 2 Chung Shan North Road Taipei, Taiwan R.O.C. Tel: 886-2-2523-6368 Fax: 886-2-2523-6369
SALES OFFICES AMERICAS
Americas Headquarters Clare 78 Cherry Hill Drive Beverly, MA 01915 Tel: 1-978-524-6700 Fax: 1-978-524-4900 Toll Free: 1-800-27-CLARE Eastern Region Clare P.O. Box 856 Mahwah, NJ 07430 Tel: 1-201-236-0101 Fax: 1-201-236-8685 Toll Free: 1-800-27-CLARE Central Region Clare Canada Ltd. 3425 Harvester Road, Suite 202 Burlington, Ontario L7N 3N1 Tel: 1-905-333-9066 Fax: 1-905-333-1824 Western Region Clare 1852 West 11th Street, #348 Tracy, CA 95376 Tel: 1-209-832-4367 Fax: 1-209-832-4732 Toll Free: 1-800-27-CLARE Canada Clare Canada Ltd. 3425 Harvester Road, Suite 202 Burlington, Ontario L7N 3N1 Tel: 1-905-333-9066 Fax: 1-905-333-1824
http://www.clare.com
Clare cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in this Clare product. No circuit patent licenses nor indemnity are expressed or implied. Clare reserves the right to change the specification and circuitry, without notice at any time. The products described in this document are not intended for use in medical implantation or other direct life support applications where malfunction may result in direct physical harm, injury or death to a person.
Specification: DS-MXED101-R9 (c)Copyright 2000, Clare, Inc. All rights reserved. Printed in USA. 3/7/01

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